This invention relates generally to logic interface or conversion circuits and more particularly, it relates to a logic interface circuit which recovers phase and data from a data/frequency signal having distorted duty cycles caused by an ECL-to-CMOS translator.
As is generally well-known in the art, various types of digital logic circuitry are widely used in the area of computer data processing systems in different parts of the processing system. In order to transfer data from one part of the processing system having one logic type (i.e., ECL) of integrated circuit devices to another part having another logic type (i.e., CMOS) of integrated circuit devices, there is often required a translation from one logic type to the other type since they have different switching speeds and the input/output voltages corresponding to high and low logic levels are different.
For example, bipolar emitter-coupled logic (ECL) voltage levels have a small voltage swing (about 0.8 volts) and complementary metal-oxide semiconductor (CMOS) voltage levels have a larger voltage swing (approximately 5.0 volts. Since many of these processing systems are designed with both ECL and CMOS logic circuits, there are required interface circuits such as ECL-to-CMOS translators so that these two different types of logic circuits will be compatible with each other. In other words, the ECL-to-CMOS translators are used to shift the level of the ECL input logic signals to a level which will be recognized by the CMOS logic circuits.
Unfortunately, because of variations in process parameter, power supply, temperature and manufacturing tolerances, such ECL-to-CMOS translators that perform the conversion will not, in many cases, provide the desired, symmetrical CMOS output signal V.sub.out1 having equal rise and fall times as shown in FIG. 1(b). The actual CMOS output signal V.sub.out2 will become distorted or non-symmetrical as shown in FIG. 1(c). When the ECL input signal is in the form of ECL differential input signals V.sub.in+ and V.sub.in- of FIG. 1(a), which are used to carry both data information and the clock frequency of a system referred to sometimes as a "Non Return to Zero, Invert on Ones" (NRZI) or data/frequency signal, the non-symmetry in the CMOS output signal caused by the translator will result in inaccurate detection of the clock frequency.
Accordingly, there are has arisen a need in the industry to provide a logic interface circuit which recovers phase and data from a data/frequency signal having distorted duty cycles caused by an ECL-to-CMOS translator. The logic interface circuit of the present invention receives ECL differential input signals of the NRZI type and generates an output signal which is CMOS compatible so that both data and frequency information can be easily extracted separately.